As IC’s get more powerful to meet consumer demand and this same demand drives the prices ever lower, semiconductor device manufacturers are faced with one of the toughest challenges yet to emerge in their business. How do we continue to drive down the costs of these new chips when each new version becomes more complex to test and requires increasingly powerful testers?

If we look at the basic steps of designing a new IC, we can break the process down into three (3) basic steps: 1) the silicon design, 2) the device fabrication and assembly, and 3) the final testing. Over the past 10+ years, the silicon designers have done a great job in adopting standards for their CAE tools. It is now possible to use “Best in Class” design tools because of the extensive use of standards between various CAE suppliers. Likewise, in the fabrication area, standards have played a large part in reducing the cost of building the chips. 300mm wafers are now mainstream and FOUP’s (Front Opening Unified Pods) allow wafers to be easily moved from machine to machine in the fab. All of this has worked to lower the cost of design and fabrication. But when it comes to final production testing of the IC’s, we have an altogether different story. Because of a lack of standards and the increasing complexity of the IC’s being demanded by the marketplace, the cost of test has continued to escalate, not decrease.

Studies have shown that packaging and test now account for, on average, about 50% of the total product cost for an IC; and this number is projected to rise to over 75% within the next few years. The rising cost of semiconductor device testing is now one of the main challenges to manufacturers.

How are manufacturers addressing this new challenge? There are three (3) major trends that are now emerging:

  1. Strip testing allows devices to be production final tested in a massively parallel configuration while still in their leadframe or laminate array rather than one (or a few) at a time. Increased tester utilization of 10%-15%, higher first pass yields of 2%-4%, higher parallelism, far less jams and the ability to handle very small parts (3mmx3mm and below) are documented benefits of moving to strip testing over singulated testing. Strip testing is not for every device, but for those devices (and volumes) that make sense, strip test is a proven way to dramatically reduce the costs of test, often by as much as 40% or more.

    A major benefit of strip testing is that it eliminates the need to handle the individual devices. This is important since devices are getting smaller and thinner to meet market demands. It’s virtually impossible to reliably handle devices smaller than 3mm x 3mm with a gravity handler due to the high jam rates. Even pick-and-place and turret type handlers face difficulties with such small devices. Strip test handlers, in comparison, are regularly handling parts as small as 0.3mm x 0.6mm and testing over 100 devices in parallel without jams since they handle the strip instead of the individual devices.

  2. Higher parallelism during testing of singulated devices is also becoming more widely used. While it clearly has benefits in some cases, it also suffers from the fact that high parallelism test handlers (either gravity or pick-and-place) for singulated parts are increasingly expensive as compared to traditional singulated handlers and are still generally limited to parallelism of 32-up and below. Some manufacturers now report that their capex budget for “test” is now almost equally split between testers and test handlers. This is because testers are generally decreasing in cost while traditional singulated and pick-and-place test handlers are generally increasing in cost. This increasing cost for test handlers is due to a desire for higher parallelism and for the ability to handle ever decreasing device sizes.

  3. Wafer probe has always been a key part of the IC testing process. Initially, probe (or wafer sort) was used for two purposes; first to screen out bad devices and therefore save on the cost of packaging those devices, and second, to give the ability to provide fast yield feedback to the wafer fab. Now, some manufacturers are attempting to expand probe so that it actually substitutes for final test. Much of this initiative is driven by the market demand to sell die instead of packaged parts. This in turn demands that die have the best quality possible which means full functional testing at wafer probe. Commonly referred to as KGD (Known Good Die), these die will a) get packaged by an end user in some type of custom package; or b) get mounted directly onto a substrate; or c) get combined with other die into a multi-chip package or MCP.

    Improvements in wafer probe with higher parallelism and increased accuracy have helped give rise to the concept of Wafer Level Packaging (WLP). In an effort to drive down the costs of a new device by eliminating the traditional plastic packaging, manufacturers are turning to WLP. In WLP, the device is singulated and then fully functionally tested, with higher levels of parallelism, at wafer probe and shipped to the customer for direct mounting on the PC board. The economics of WLP are rapidly approaching the point that makes it cost effective as compared to traditional packaging.

At the end of the day, we are seeing a dramatic change in how testing of IC’s is accomplished. With the costs of test now accounting for a large share of the total device cost, IC manufacturers must look at replacing the 30 year old singulated testing technologies that had served them well until recently. It’s no longer reasonable or feasible to expect that those old technologies will meet the demands of an increasingly complex and competitive industry. Higher parallelism, either for final packaged devices or for wafer level products, will be an indispensable part of any successful test organization, because it has been proven to drive down the cost of test… and make those “must have” consumer appliances more affordable for all of us.